This disclosure relates to a semiconductor device and is applicable to a semiconductor device, for example, having a degradation stress detection function.
Japanese Unexamined Patent Application Publication No. 2004-266243 describes: “The first test structure is, to monitor the hot carrier degradation. The circuit is formed by two ring oscillators: one receives the hot carrier effect (degradation ring oscillator) in the transistor, and the other is not subject to the hot carrier effect (non-degradation ring oscillator). At first, each of the both ring oscillators has a predetermined frequency. The both frequencies do not have to be identical. Degradation ring oscillator is applied to an input of a binary counter. Non-degradation ring oscillator frequency is divided into lower frequency. The divided frequency is, in one state, to gate the binary counter on and, in another state, to reset the counter. Just after the fabrication, the binary counter detects a finite count number “i” during each gate cycle. When the degradation ring oscillator frequency is reduced due to the hot carrier effect, the binary counter detects a decrease of pulse applied at some point, and as the result, the count becomes “j” (j<i). A designer determines a degradation difference (i−j) that matters from the viewpoint of reliability; when the (i−j) exceeds a predetermined limit, the circuit is then to create an end of life signal.”
Japanese Unexamined Patent Application Publication No. 2011-227756 describes: “A terminal device is provided with a high temperature detection counter circuit that detects a temperature of the device, integrates the stress accelerating time weighted according to the detected temperature as a stress count value, and outputs an interrupt signal when the stress count value gets a predetermined value and more, and a CPU of controlling the operation of the device. When the total value of a cumulative stress accelerating time obtained by cumulatively counting the interrupt signal from the high temperature detection counter circuit and a system time from a timer circuit exceed a set stress management time, the CPU performs rewriting into a non-volatile memory.”